台灣留學生出席國際會議補助

2010年4月27日星期二

A Systolic Array for Linear MIMO Detection Based on an All-Swap Lattice Reduction Algorithm

論文發表人:王迺鈞/加州大學洛杉磯分校/電機系
 
 
多輸入輸出天線通訊系統(MIMO)可提供高速率傳輸以及提高抗雜訊能力,然而相對的在接收端的訊號偵測也有相當高的複雜度。對於有即時處理(real-time)需求的系統而言,無疑的需要相當高的硬體需求。本論文提出以脈動陣列為架構的晶格優化(lattice reduction)訊號偵測方法。在晶格優化訊號偵測法中,每當傳輸通道的特性改變,接收端就必須重新計算新的優化晶格。在高速行動通訊中,通道特性通常非常迅速的改變,因此接收端必須非常快速的計算優化晶格。而脈動陣列是一種簡易的平行處理架構,其特性在於使用多個簡易的運算元同時運作來提高輸出效率,因此在使用高運算能力的硬體下亦能提供高速的運算。本論文亦提出適合平行處理的晶格優化演算法,相較於過去文獻中常用的LLL晶格優化法,本論文的方法運用在脈動陣列上有相當優異的效能表現。
 
A systolic array to implement lattice-reduction-aided linear detection is proposed for a MIMO receiver. The lattice reduction algorithm and the ensuing linear detections are operated in the same array, which can be hardware-efficient. All-swap lattice reduction algorithm (ASLR) is considered for the systolic design. ASLR is a variant of the LLL algorithm, which processes all lattice basis vectors within one iteration. Lattice-reduction-aided linear detection based on ASLR and LLL algorithms have very similar bit-error-rate performance, while ASLR is more time efficient in the systolic array, especially for systems with a large number of antennas.